Complete Digital Logic Notes for GATE CSE 2026 – Best Notes

Digital Logic GATE CSE ka sabse scoring subject hai. Har saal 4-5 marks aate hain aur sabse easy hota hai. Isme K-Map, Combinational Circuit aur Sequential Circuit se direct question aate hain. Agar aapne ye 3 chapter pakka kar liye to 5 marks pakke.

1. Number System and Boolean Algebra – Base

Number System: Binary, Octal, Hexadecimal conversion aana chahiye. 2’s Complement se Negative number represent karte hain. Range: -2^(n-1) to 2^(n-1)-1. GATE me 2’s complement ka addition/subtraction har saal poochte hain.

Boolean Algebra: a + a’ = 1, a.a’ = 0. De Morgan Law: (A+B)’ = A’.B’ aur (A.B)’ = A’+B’. Consensus Theorem: AB + A’C + BC = AB + A’C. Ye theorem K-Map solve karne me kaam aata hai.

2. K-Map and Minimization – Har Saal 2 Marks

K-Map se Boolean Expression ko minimize karte hain. 2 Variable me 4 cells, 3 Variable me 8 cells, 4 Variable me 16 cells.

GATE Trick: K-Map me Group 2^n me banta hai (1,2,4,8). Don’t Care (X) ko 1 maan sakte hain agar group bada ho raha hai. Prime Implicant aur Essential Prime Implicant ka difference yaad rakho. Essential PI wo hai jo ek hi 1 ko cover kar raha hai.

Quine-McCluskey Method: 5 se zyada variable ke liye K-Map fail ho jata hai, tab Q-M method use hota hai.

3. Combinational Circuits – Most Important

Isme Output sirf Present Input par depend karta hai, Memory nahi hoti.

• Half Adder/Full Adder: Half Adder: Sum = A xor B, Carry = AB. Full Adder: Sum = A xor B xor C, Carry = AB+BC+AC. n-bit Adder me n Full Adder lagte hain.
• Multiplexer (MUX): 2^n:1 MUX. n Select line. 4:1 MUX se koi bhi 2 variable ka function implement ho sakta hai. GATE me MUX se Function implement karna har saal aata hai.
• Decoder: MUX ka opposite. n:2^n. 2:4 Decoder se 2:1 MUX bana sakte hain.
• Comparator, Encoder, Code Converter: Binary to Gray, Gray to Binary conversion.

Formula: n variable ke liye MUX chahiye to 2^(n-1):1 MUX + 1 NOT gate chahiye hota hai.

4. Sequential Circuits – Latch vs Flip-Flop

Output Present Input + Past State par depend karta hai. Memory element hota hai.

Latch vs Flip-Flop: Latch Level Triggered, Flip-Flop Edge Triggered. Latch me Racing problem hoti hai.

SR Flip-Flop: S=1,R=1 Invalid State. Is problem ko JK me solve kiya. JK me J=K=1 to Toggle hota hai. Is Toggle se Race Around Condition hoti hai, isko Master-Slave JK se solve karte hain.

D Flip-Flop: Sabse zyada use hota hai. D = Next State. Register isi se bante hain.

T Flip-Flop: T=1 to Toggle. Counter isi se banta hai. T=0 to No Change.

Excitation Table: GATE me Flip-Flop conversion (SR to JK, JK to D) poochte hain. Excitation Table yaad hona chahiye.

5. Counters and Registers

Registers: SISO, SIPO, PISO, PIPO. 4-bit SISO me 4 Clock Pulse lagenge data store karne me.

Counters:

• Asynchronous (Ripple) Counter: Clock sabko alag milta hai. Delay zyada hota hai. n Flip-Flop se 2^n Mod Counter. Mod-5 ke liye 3 FF chahiye (2^2=4 <5, 2^3=8>=5).
• Synchronous Counter: Sabko ek hi Clock. Speed fast. Design ke liye Excitation Table use hoti hai.
• Ring Counter: n FF se n States. Mod = n.
• Johnson Counter: n FF se 2n States. Mod = 2n.

GATE Trick: Agar Counter me koi Unused State hai to wo Lockout me ja sakta hai. Lockout se bachne ke liye Unused state ko Used state par le jana chahiye.

Final Checklist: MUX se Function Implementation, K-Map (4 Variable), Counter Mod, Race Around Condition – Ye 4 topic pakka kar lo.