Complete COA Notes for GATE CSE 2026 – Full Revision

COA (Computer Organization and Architecture) GATE ka sabse tough aur numerical wala subject hai. Har saal 5-7 marks aate hain. Pipelining aur Cache se to har saal 3 marks pakke hain. Ye notes aapko Topper ke notes se banaye gaye hain.

1. Number Representation and ALU

Fixed Point: Sign Magnitude me 2 Zero (+0,-0). 1’s Complement me bhi 2 Zero. 2’s Complement me 1 hi Zero, isliye sabse zyada use hota hai. Overflow tab hota hai jab Carry In != Carry Out.

Floating Point (IEEE 754): Single Precision: 1 Sign + 8 Exponent + 23 Mantissa. Double: 1+11+52. Bias: Single me 127, Double me 1023. GATE me iska conversion aur Range poochte hain.

ALU: Booth’s Algorithm Multiplication ke liye. Restoring aur Non-Restoring Division.

2. Instruction Set and Addressing Modes

Addressing Modes: GATE me Effective Address nikalna poochte hain.

• Immediate: Data instruction me hi hai. Fastest.
• Direct: Address diya hai.
• Indirect: Address ke andar Address.
• Register Indirect: Register me Address hai.
• Indexed: EA = Base + Index.
• PC Relative: EA = PC + Offset. Branch instruction me use hota hai.

Control Unit: Hardwired fast hota hai, RISC me use hota hai. Microprogrammed slow lekin flexible, CISC me use hota hai.

3. Pipelining – Har Saal 2 Marks Pakka

Pipelining me Instruction ko 5 Stage me baat dete hain: IF, ID, EX, MEM, WB. Har stage ek clock cycle leta hai.

Speedup Formula: Speedup = (n*k) / (k + n -1). jahan k=Stages, n=Instructions. Ideal Speedup = k.

Hazards: Ye GATE ka favorite hai.

1. Structural Hazard: Hardware Resource kam hai. Solution: Resource duplicate karo.
2. Data Hazard: Ek instruction dusri ka data use kar rahi hai. RAW, WAR, WAW. Solution: Forwarding/Bypassing, Stalling (Bubble Insert).
3. Control Hazard (Branch Hazard): Branch instruction ki wajah se. Solution: Branch Prediction, Delayed Branch, Flushing.

GATE Trick: Data Hazard me kitne Stall/Bubble lagenge, ye poochte hain. Agar Forwarding hai to 1 Stall kam ho jayega.

4. Memory Hierarchy – Cache Numerical

Memory: Register < Cache < Main Memory < Disk. Cache ka Access Time sabse kam.

Cache Mapping:

• Direct Mapping: Block j = i mod m. Simple lekin Conflict Miss zyada.
• Fully Associative: Kahi bhi rakh sakte hain. Search slow. No Conflict Miss.
• k-way Set Associative: Best of both. Direct + Fully ka mix. GATE me 2-way, 4-way poochte hain.

Important Formulas:

• Cache Size = Number of Blocks * Block Size
• Tag Bits = Physical Address Bits – (Index Bits + Offset Bits)
• Average Access Time (AMAT) = Hit Time + Miss Rate * Miss Penalty
• 2 Level Cache: AMAT = L1 Hit + L1 Miss Rate*(L2 Hit + L2 Miss Rate*Memory Time)

Cache Write Policy: Write Through (RAM me bhi likho + Dirty Bit nahi) aur Write Back (Sirf Cache me likho, Dirty Bit use hota hai, Replacement par RAM me likhte hain).

5. I/O and Secondary Memory

I/O Modes: Programmed I/O (CPU wait karta hai), Interrupt Driven (CPU dusra kaam karta hai), DMA (Direct Memory Access – Sabse Fast, CPU ka use nahi).

DMA: 2 Mode: Burst Mode (Full control DMA ka) aur Cycle Stealing (Ek-ek word transfer).

Final Formula Sheet for COA: Pipelining Speedup, AMAT, Cache Tag Bits, IEEE 754 Bias. Ye 4 formula se 4 marks pakke.

Agla Subject Computer Networks ka chahiye to bolo bhai, wo bhi ready hai.